{"created":"2023-06-26T10:41:36.165361+00:00","id":2393,"links":{},"metadata":{"_buckets":{"deposit":"039d43e3-7a1f-42e9-813d-6ce7ab813697"},"_deposit":{"created_by":15,"id":"2393","owners":[15],"pid":{"revision_id":0,"type":"depid","value":"2393"},"status":"published"},"_oai":{"id":"oai:hi-tech.repo.nii.ac.jp:00002393","sets":["442:452"]},"author_link":["2742","5095","5349"],"item_10002_biblio_info_7":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicPageEnd":"92","bibliographicPageStart":"89","bibliographicVolumeNumber":"4","bibliographic_titles":[{"bibliographic_title":"八戸工業大学異分野融合科学研究所紀要"},{"bibliographic_title":"The bulletin of Reseach Institute for Interdisciplinary Science, Hachinohe Institute of Technology","bibliographic_titleLang":"en"}]}]},"item_10002_description_12":{"attribute_name":"論文ID（NAID）","attribute_value_mlt":[{"subitem_description":"110004623033","subitem_description_type":"Other"}]},"item_10002_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"In the sensor feedback control of intelligent robots, the delay time must be reduced for a large number od multioperand multiply-additions. To reduce the delay time for the multiply-additions, the architecture of the dynamically reconfigurable parallel VLSI processors are proposed. In each processor element (PE), a switch circuit is provided to change the direct connection between the multipliers and adders,so that the overhead in data transfer is reduced. In this paper, we report the delay time of the switch circuit based on a 0.18μm CMOS design rule.","subitem_description_type":"Abstract"}]},"item_10002_full_name_3":{"attribute_name":"著者別名","attribute_value_mlt":[{"affiliations":[{"affiliationNames":[{"affiliationName":"八戸工業大学","lang":"ja"}],"nameIdentifiers":[]}],"familyNames":[{"familyName":"FUJIOKA","familyNameLang":"en"},{"familyName":"藤岡","familyNameLang":"ja"},{"familyName":"フジオカ","familyNameLang":"ja-Kana"}],"givenNames":[{"givenName":"YOSHICHIKA","givenNameLang":"en"},{"givenName":"与周","givenNameLang":"ja"},{"givenName":"ヨシチカ","givenNameLang":"ja-Kana"}],"nameIdentifiers":[{"nameIdentifier":"5095","nameIdentifierScheme":"WEKO"},{"nameIdentifier":"read0183435","nameIdentifierScheme":"researchmap","nameIdentifierURI":"https://researchmap.jp/read0183435"}],"names":[{"name":"FUJIOKA, YOSHICHIKA","nameLang":"en"},{"name":"藤岡, 与周","nameLang":"ja"},{"name":"フジオカ, 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